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AT1362a/b preliminary product information synchronous buck converter with power good detector & ldo 7f, no.9, park avenue ii, science-based industrial park, hsinchu 300,taiwan, r.o.c. tel: 886-3-563-0878 fax: 886-3-563-0879 www: http://www.aimtron.com.tw 5/30/2006 rev:1.0 email: service@aimtron.com.tw 1 features ? operation voltage 2.5v~6.0v ? oscillation frequency 1mhz ? output current maximum 400ma dc-dc converter ? built-in 400ma/ldo ? power good indicator with time delay adjustable ? built-in current limit ? built-in uvlo ? built-in thermal shutdown applications ? power supply for slim type devices general description the AT1362a/b provides complete control for a dc/dc converter optimized for high-performance microprocessor applications. it consists of a synchronous step-down dc/dc converter and a high-speed ldo regulator connected in series with the dc/dc converter output. a power good detector and ldo on/off control is also built-in(metal option). dc/dc converter is operated on current mode architecture for excellent line and load transient response. 1mhz operation frequency is allowing the use of small surface mount inductor and capacitor. the internal synchronous switch increases efficiency and eliminates the need for an external schottky diode. the AT1362a/b is a family of low-noise synchronous step-down dc/dc converters that is ideally suited for systems powered form a 1-cell li-ion battery or from a 3-cell to 4-cell nicd, nimh, or alkaline battery. it can also be used to usb-based power system. block diagram current sense osc + slope r s q sw vref + - vcc pgnd shoot throught pg delay out2 out1 + - vref current limit 5 uvlo vreg vref - + 0.7v r2 r1 uvlo *out1=2.5v/1.8v metal option auto discharge vcc 0.7 r4 r3 1ua vbg vbg agnd + - + - ctl bpc aimtron reserves the right without notice to change this circuitry and specifications.
AT1362a/b preliminary product information synchronous buck converter with power good detector & ldo 7f, no.9, park avenue ii, science-based industrial park, hsinchu 300,taiwan, r.o.c. tel: 886-3-563-0878 fax: 886-3-563-0879 www: http://www.aimtron.com.tw 5/30/2006 rev:1.0 email: service@aimtron.com.tw 2 pin assignment 1 2 3 4 5 6 7 8 AT1362 9 10 AT1362a AT1362b dc/dc 2.5v dc/dc 1.8v ldo 3.3v ldo 3.3v dfn10 (top view) ordering information a:1362an b:1362bn date code * for more marking information, contac t our sales representative directly. pin description symbol pin no. descript 1 pg power good indicator output(ative hi) 2 out1 dc/dc output (2.5v or 1.8v) 3 vcc power supply 4 sw dc/dc inductor node 5 pgnd power ground 6 vbg reference output voltage 7 agnd analog ground 8 delay the capacitor connection terminal for ldo control and pg delay time setup 9 out2 ldo output (3.3v) 10 bpc ldo input by-pass capacitor node bottom gnd analog ground part number package marking 1362 n dfn10,green
AT1362a/b preliminary product information synchronous buck converter with power good detector & ldo 7f, no.9, park avenue ii, science-based industrial park, hsinchu 300,taiwan, r.o.c. tel: 886-3-563-0878 fax: 886-3-563-0879 www: http://www.aimtron.com.tw 5/30/2006 rev:1.0 email: service@aimtron.com.tw 3 absolute maximum ratings * 1 rated value parameter symbol min. max. unit power supply voltage vcc -0.3 +6.5 v out1, out2 -0.3 vcc v input pin voltage sw, pg -0.3 vcc+0.3 v p-channel switch source current (dc) ? - 0.5 a n-channel switch sink current (dc) ? - 0.5 a peak sw sink and source current ? - 0.75 a thermal resistance from junction to ambient ja dfn10 - 35.25 0 c/w thermal resistance from junction to case jc dfn10 - 3 0 c/w operating temperature t a ? -20 +85 0 c storage temperature ? -20 +150 0 c hbm - 2 kv esd susceptibility*2 mm - 200 v 1. stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability . 2. device are esd sensitive. handling precaution recommended. the human body model is a 100pf capacitor discharged through a 1.5k ? resistor into each pin. recommended operating conditions (ta=+25 0 c) values parameter symbol min. typ. max. unit power supply voltage v in 2.5 -- 6.0 operating temperature* t op -20 +25 +85 c operating junction temperature t j - - +150 c * using x5r or x7r input capacitors.
AT1362a/b preliminary product information synchronous buck converter with power good detector & ldo 7f, no.9, park avenue ii, science-based industrial park, hsinchu 300,taiwan, r.o.c. tel: 886-3-563-0878 fax: 886-3-563-0879 www: http://www.aimtron.com.tw 5/30/2006 rev:1.0 email: service@aimtron.com.tw 4 electrical characteristics (vcc = 3.6v,t a =+25 , unless otherwise noted. ) values parameter symbol condition min. typ. max. unit dc/dc converter vcc uvlo v uv vcc=3v 2v sweep - 2.4 - v uvlo hysteresis width v uvhy - 100 - mv input supply range v cc 2.5 - 6.0 v quiescent current i s active mode - 500 - a output1 voltage accuracy v out1 -2 - +2 % output1 voltage line-regulation v out1-line vcc=3.5v to 6.0v - 0.1 0.5 % output1 variation with temperature t a =-20 to +85 - 0.5 1.0 % feedback current i out1 - 6 - ua current limit i cl1 vin=5v, v out1 =2.5v /1.8v 0.6 0.7 0.8 a maximum output current i o vin=5v, v out1 =2.5v /1.8v , l=4.7uh 400 - - ma fosc1 vout1=2.5v /1.8v 0.8 1.0 1.2 mhz oscillator frequency fosc2 vout1=0v - 200 -- khz r ds(on) of p-channel mosfet r pfet i lx = 300ma - 0.3 0.4 ? r ds(on) of n-channel mosfet r nfet i lx = -300ma - 0.25 0.35 ? sw leakage current i swl - 0.1 1 a control block pg on voltage v pgon i pg =1ma - - 0.4 v pg hysteresis width v pgthys - 80 - mv pg pin leak current i pgtlk v pg =5.0v - - 1 ua ldo control on hysteresis width v ldthys - 80 - mv delay pin charge current i delay 0.8 1.0 1.2 ua ldo output2 voltage accuracy v out2 -2 - +2 % current limit i cl2 450 - - ma dropout voltage v dv i out2 =400ma - 400 600 mv load regulation ? v out2 i out2 =1ma 100ma - 15 50 mv line regulation lr i out2 =100ma, v out1 =3.6v 6.0v - 0.05 0.25 % ripple rejection rate psrr i out2 =100ma, f=1khz - 60 - db out2 leakage current i out2lk - 6 - ua
AT1362a/b preliminary product information synchronous buck converter with power good detector & ldo 7f, no.9, park avenue ii, science-based industrial park, hsinchu 300,taiwan, r.o.c. tel: 886-3-563-0878 fax: 886-3-563-0879 www: http://www.aimtron.com.tw 5/30/2006 rev:1.0 email: service@aimtron.com.tw 5 typical characteristics efficiency vs. output1 current 50 55 60 65 70 75 80 85 90 95 100 10 100 1000 output1 current(ma) efficiency(%) l=2.2uh l=3.3uh l=4.7uh l=6.8uh ch1 vin, ch2 vo u t 1 ch3 vo u t 2 , c h 4 pg ch1 vo u t 1 , c h 2 vo u t 2 , c h 4 iout1 iout1=100ma~300ma, iout2=200ma efficiency vs. output1 current 50 55 60 65 70 75 80 85 90 95 100 10 100 1000 output1 current(ma) efficiency(%) vin=5.0v vin=4.2v vin=3.8v vin=3.6v ch1 delay, ch2 vo u t 1 ch3 vo u t 2 , c h 4 pg ch1 vo u t 1 , c h 2 vo u t 2 , c h 4 iout2 iout1=200ma, iout2=100ma~300ma vin=5v vout1=1.8v vout1=1.8v l=4.7uh
AT1362a/b preliminary product information synchronous buck converter with power good detector & ldo 7f, no.9, park avenue ii, science-based industrial park, hsinchu 300,taiwan, r.o.c. tel: 886-3-563-0878 fax: 886-3-563-0879 www: http://www.aimtron.com.tw 5/30/2006 rev:1.0 email: service@aimtron.com.tw 6 typical application circuits 5v 2.5v 1.8v 3.3v vdely pg 90% 90% 0.7v 0.7v uvlo t1 t2 timing of power-on sequencing
AT1362a/b preliminary product information synchronous buck converter with power good detector & ldo 7f, no.9, park avenue ii, science-based industrial park, hsinchu 300,taiwan, r.o.c. tel: 886-3-563-0878 fax: 886-3-563-0879 www: http://www.aimtron.com.tw 5/30/2006 rev:1.0 email: service@aimtron.com.tw 7 typical application circuits ( continued ) sw bpc vcc pgnd pg delay out2 out1 to dsp vin 5.0v vout1 2.5v/400ma vout2 3.3v/400ma 10uf 4.7uh 10uf AT1362a 10nf 2.2uf vbg 10nf agnd 100k 0.1uf figure 1 sw vcc pgnd pg out2 out1 vin 5.0v vout1 1.8v/400ma vout2 3.3v/400ma 10uf 4.7uh 10uf AT1362b 2.2uf to dsp 100k bpc delay 10nf vbg 10nf agnd 0.1uf figure 2
AT1362a/b preliminary product information synchronous buck converter with power good detector & ldo 7f, no.9, park avenue ii, science-based industrial park, hsinchu 300,taiwan, r.o.c. tel: 886-3-563-0878 fax: 886-3-563-0879 www: http://www.aimtron.com.tw 5/30/2006 rev:1.0 email: service@aimtron.com.tw 8 application information capacitor selection in continuous mode, the source current of the top mosfet is square wave of duty cycle. the primary function of the input capacitor is to provide a low impedance loop for the edges of pulsed current drawn by th e AT1362a/b. a load step at the output can induce ringing at the input vin. this ring ing can couple to the output and be mistaken as loop instability. the oscillation can be imp roved by add the capacitance of the input capacitor. a typical value is 10 f ceramic (x5r or x7r), poscap or aluminum polymer. these capacitors will provide good high frequency bypassing and their low esr will reduce resistive losses for high er efficiency. the input capacitor rms current varies with the input voltage a nd the output voltage. the equation for the maximum rms current in the input capacitor is: the output capacitor depends on the suitabl e ripple voltage. low ripple voltage corresponds to lower effective series resi stance (esr). the output ripple voltage is determined by: the output capacitor rms ripple current is given by: vbg capacitor a vbg pin is provided to decouple the bandgap reference voltage. an external capacitor connected form vbg to gnd re duces noise present on the internal reference voltage, which in turn significan tly reduces output noise and also improves psrr. larger capacitor values may be used to further improve psrr, but result in a longer time period (slower turn on) to settle output voltage when power is initially applied. ) 1 ( in o in o omax rms v v v v i i ? = ) 8 1 ( out l out fc esr i v + ? ? ? in out in out rms v f l v v v i ? = ) ( 3 2 1
AT1362a/b preliminary product information synchronous buck converter with power good detector & ldo 7f, no.9, park avenue ii, science-based industrial park, hsinchu 300,taiwan, r.o.c. tel: 886-3-563-0878 fax: 886-3-563-0879 www: http://www.aimtron.com.tw 5/30/2006 rev:1.0 email: service@aimtron.com.tw 9 ldo for general purposes, use a 2.2uf capacitor on the ldo output. larger capacitor values and lower esr provide better supply noise rejection and transient response. a higher value input capacitor may be necessary if large, fast transients are anticipated . ceramic capacitors have the lowest esr, and will offer the best ac performance. when choosing the input and output ceramic capacitors, choose the x5r or x7r dielectric formulations. these dielectrics have the best temperature and voltage characteristics of all the ceramics for a given value and size. inductor selection the inductor is chosen based on the desire d ripple current. large value inductors lower ripple current and small value inductors result in higher ripple current. always consider the losses associated with the dcr and its effect on the total converter efficiency when selecting an inductor. the inductor is selected to limit the ripple current to some predetermined value, typically 20~40% of the full load current at the maximum input voltage. the formula of inductance value is as below: ) ( 4 . 0 ~ 2 . 0 max out l i i = ? ? ? ? ? ? ? ? ? ? ? = in out l out v v i f v l 1 l t v v i i i i on out in o l o pk ? + = ? + = 2 ) ( 2 power good indicator with adjustable time delay when out1 pin is above 2.25v or 1.62v (typ.) and with a delay time (t1) the out2 is start to regulation. the pg pin terminal is an open drain output of n-mos. connect a resistor from pg pin to vcc or out2 to create a logic signal. if out2 pin is less than 2.97v (typ.) this pin is pulled to ground. when out2 pin is above 2.97v (typ.) and with a delay time (t2) this pin is open. pg pin is forced low when in uvlo. the formula of adjustable delay time is as below: delay i v c t t time delay 7 . 0 2 1 = = = ?
AT1362a/b preliminary product information synchronous buck converter with power good detector & ldo 7f, no.9, park avenue ii, science-based industrial park, hsinchu 300,taiwan, r.o.c. tel: 886-3-563-0878 fax: 886-3-563-0879 www: http://www.aimtron.com.tw 5/30/2006 rev:1.0 email: service@aimtron.com.tw 10 the dissipation the power loss is given by: in s s f r out in n on ds out p on ds out dc dc loss v i f t t i v d r i d r i p + + + ? + = ? ? ? ) ( ) 1 ( 1 ) ( 2 1 ) ( 2 1 ) ( ) ( 2 2 ) ( out in out ldo loss v v i p ? = ) ( ) ( ) ( ) ( ldo loss dc dc loss ja a max j p p t t + + = ? inductors surface mount inductance( h) manufacturer/part no. manufacturer website 3.3 sumida cdrh4d28-3r3 4.7 sumida cdrh5d18-4r7 www.sumida.com 3.3 mitsumi c3-k1.8l-3r3 mitsumi c4-k1.8l-3r3 www.mitsumi.co.jp 3.3 abc sh40283r3ysb 4.7 abc sh40284r7ysb www.atec-group.com capacitors surface mount capacitance( f) manufacturer/part no. manufacturer website 22 tdk c3216x5r0j226m www.tdk.com 47 tdk c3225x5r0j46m www.tdk.com 10 grm42-6x5r 106k6.3 www.murata.com 2.2 taiyo lmk212bj225md www.t-yuden.com 4.7 taiyo jmk212bj475mg www.t-yuden.com
AT1362a/b preliminary product information synchronous buck converter with power good detector & ldo 7f, no.9, park avenue ii, science-based industrial park, hsinchu 300,taiwan, r.o.c. tel: 886-3-563-0878 fax: 886-3-563-0879 www: http://www.aimtron.com.tw 5/30/2006 rev:1.0 email: service@aimtron.com.tw 11 pc board layout 1. the most critical aspect of the layout is the placement of the input capacitor c2. it must be placed as close as possible to the AT1362a/b to reduce the input ripple voltage. 2. power loops on the input and output of the converter should be laid out with the shortest and widest traces possible. the longer and narrower the trace, the higher resistance and inductance it will have. the length of traces in series with the capacitors increases its esr and esl and reduces their effectiveness at high frequency. 3. the out1 pin should connect to c1 direct ly. and the route should be away from the noise source, such as inductor of sw line. 4. grounding all components at the same point may effectively reduce the occurrence of loop.
AT1362a/b preliminary product information synchronous buck converter with power good detector & ldo 7f, no.9, park avenue ii, science-based industrial park, hsinchu 300,taiwan, r.o.c. tel: 886-3-563-0878 fax: 886-3-563-0879 www: http://www.aimtron.com.tw 5/30/2006 rev:1.0 email: service@aimtron.com.tw 12 package outline : dfn10
AT1362a/b preliminary product information synchronous buck converter with power good detector & ldo 7f, no.9, park avenue ii, science-based industrial park, hsinchu 300,taiwan, r.o.c. tel: 886-3-563-0878 fax: 886-3-563-0879 www: http://www.aimtron.com.tw 5/30/2006 rev:1.0 email: service@aimtron.com.tw 13 reflow condition (ir/convection or vpr reflow ) classification reflow profiles profile feature sn-pb eutectic assembly pb-free assembly average ramp-up rate (t l to t p ) 3 c/second max. 3 c/second max. preheat -temperature min(tsmin) -temperature max (tsmax) -time (min to max)(ts) 100 c 150 c 60-120 seconds 150 c 200 c 60-180 seconds time maintained above: -temperature (t l ) -time (t l ) 183 c 60-150 seconds 217 c 60-150 seconds peak/classification temperature(t p ) see table 1 see table 2 time within 5 c of actual peak temperature (t p ) 10-30 seconds 10 seconds max. ramp-down rate 6 c/second max. 6 c/second max. time 25 c to peak temperature 6 minutes max. 8 minutes max. * all temperatures refer to topside of the package, measured on the package body surface. classification reflow profiles(cont.) table 1. snpb entectic process C package peak reflow temperatures package thickness volume mm 3 <350 volume mm 3 350 <2.5mm 240+0/-5 225+0/-5 2.5mm 225+0/-5 225+0/-5 table 2. pb - free process C package classification reflow temperatures package thickness volume mm 3 <350 volume mm 3 350-2000 volume mm 3 >2000 <1.6mm 260+0 260+0 260+0 1.6mm - 2.5mm 260+0 250+0 245+0 2.5mm 250+0 245+0 245+0 *tolerance: the device manufacturer/supplier shal l assure process compatibility up to and including the stated classification temperature (this means peak reflow temperature +0 ? . for example 260 ? +0 ? ) at the rated msl level.

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